Design Engineer V

Duties:





ASIC Power Engineer to perform power analysis and optimizations in ASIC for Meta’s AR/VR products.





Areas of interest include Machine Learning. Primary are Python, tcl and SystemVerilog.





 





Responsibilities:





Perform PPA optimization with Fusion compiler.





Perform RTL and netlist level Power analysis





Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction





Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)





Implement some blocks at RTL and UPF





Ability to document and communicate clearly





 





Must Have Skills:





Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules)





Should know how to use Python, Perl (or similar) scripting and data-post-processing tools





Experience in low power design, tools and methodologies including power intent UPF specifications





Silicon Power Characterization





 





Good to Have Skills:





Some power profiling experience at IP/SoC level





Experience with Silicon Power Characterization





Experience with Data analytics and visualization





 





Minimum Qualifications:





10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer





Experience with power estimation tools and synthesis, some physical design





Knowledge of power trade-offs in design and back end implementation





Hands-on experience in scripting, data analysis





BS in Electrical Engineering/Computer Science or equivalent experience





 





Qualifications:





Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules)





Python, Perl (or similar) scripting and data-post-processing tools





Excel (or Matlab) for model fitting, data visualization and analysis





Experience in low power design, tools and methodologies including power intent UPF specifications





Silicon Power Characterization





Some power profiling experience at IP/SoC level





 





 





Compensation:





The pay rate range above is the base hourly pay range that Aditi Consulting reasonably expects to pay someone for this position (compensation may vary outside of this range depending on several factors, including but not limited to, a candidate’s qualifications, skills, competencies, competencies, competencies, competencies, experience, location and end client requirements).





 





Benefits and Ancillaries:





Medical, dental, vision, PTO benefits and ancillaries may be available for eligible Aditi Consulting employees and vary based on the plan options selected by the employee.