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FPGA Design Engineer

Job Description

An FPGA Engineer with a strong academic record and with good knowledge of network protocols, communication systemsand DSP will join a thriving Technology Company. You'llberewarded with a fantastic salary package andthe option ofFully Remote or Hybrid working (1-3 daysin office per week).

About the company: Our Client is an award- winning global leader in the design and development of critical satellite communications infrastructure; enjoying continued growth and innovative technology development. They reward their loyal staff with a wealth of benefits and development opportunities, ensuring and for all.

Competencies should include:

  • Minimum of a 1st / 2.1 Bachelors Degree in Electronics related discipline.
  • Minimum of 1-3 years experience of FPGA implementation of communication systems. Recent PhDs also considered.
  • Experience working with FPGA synthesis tools such as Synplify, Vivado, Quartus.
  • Knowledge of SoC FPGAs such as Zynq or Cyclone device families.
  • DSP Algorithm implementation in Verilog.
  • Extensive experience writing FPGA test benches.

The FPGA Engineer role:

Reporting to the Digital RF Lead, the successful FPGA Engineer will be responsible for designing, developing and testing digital intermediate frequency systems utilising field-programmable-gate-arrays (FPGAs) - developing the latest digital IF distribution products for the companys extensive product portfolio. This will include producing HDL code for VITA-49 or similar network SDR transport protocols; designing and implementing digital IF algorithms and architectures using VHDL or Verilog, developing and testing FPGA firmware and software as well as performing simulation and verification of FPGA designs.

Remuneration Package:

A generous base salary will be offeredto the FPGA Engineer, with applications also welcome from Senior and Principal FPGA Engineers with fantastic salaries relative to the level of skills and experience (details on application).

Fully Remote or Hybrid working is available and flexible starting times offered to maintain a good work /life balance. Holiday starts at 25 days per year, with an option to buy / sell days and entitlement increases with length of service. There is a casual dress code, free drinks, fruit and snacks, A good Pension Plan and Annual Bonus scheme. Well-being support including free eye tests and there are discounts offered on gym membership, shopping and days out.


JBRP1_UKTJ

FPGA Design Engineer

Hereford, UK
Full time

Published on 08/03/2024

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