Functional Verification Engineer

Job summaryAdecco's client - one of the ten largest semiconductor manufacturers worldwide - market leader in automotive and power semiconductors Job Responsibilities Create and define verification plans;Develop verification environments for our ICs using Universal Verification Methodology (UVM);Draw on test scenarios using SystemVerilog;Verify functionality using the Constrained Random approach;Develop assertions in SystemVerilog for formal verification;Interact with other disciplines, such as Concept and Application Engineering, to define verification plans and strategies;Provide proactive support to users of our verification flow environment;Be responsible for our verification methods; Experience requirementsHave at least 1 years of experience in Metric Driven Verification (digital and/or mixed-signal);Have capabilities and expertise in working with microcontroller-based ICs, as well as security and safety requirements;Have excellent know-how with UVM especially using SystemVerilog;Have knowledge of firmware and RTL design (VHDL);Ideally have knowledge of Cadence verification software;