Mixed-Signal Verification Engineer - Austria

Job Title: Mixed-Signal Verification Engineer
Location: Austria
Job Type: Permanent

About the client and position:

As one of the market leaders for turnkey solutions for their broad portfolio of customers, My client offers possibility to work on many interesting and highly complex products for Automotive, Industrial, Medical and many other markets. They offer a dynamic, exciting, and friendly environment, as well as many possibilities for your further development in the direction that suits you the best.

This is a fantastic opportunity to be a part of a close team and be a driver of developing your knowledge, skills, and experience.

Responsibilities :
-Working on Verification of Analog and Mixed-Signal (AMS) products
-Develop functional models for Analog and mixed-signals IPs/blocks and ensure their matching with schematics
-Development of Analog/Mixed Mode Test-benches and verification of Analog/mixed-signals blocks and interactions between them
-Work on the verification concept and specification for our mixed-signals projects
-Align and track the implementation of test-benches and stimuli generation according to the verification plan
-Run simulations, analyze results and conduct verification reviews to ensure that requirements are met
-Shape the verification methodology in close cooperation with the application, concept and design engineers. Innovate the methodology to reduce the verification cost preserving the quality

Requirements :
-A Bachelor, Master or PhD degree in Electronics Engineering or related subject.
-Over 5 years of hands-on experience with analogue circuit layout in CMOS and Bi-CMOS technologies.
-Be a team player with good interpersonal skills, and excellent communication skills, including verbal, written and communication, and presentation skills in English.
-Very good knowledge of Cadence tool workflow for schematic capture and layout XL.
-Very good knowledge in running tool for checking DRC, LVS, ERC and antenna rules and ability to effectively debug any errors
-Very good knowledge of good layout matching techniques such as common centroid or dummy usage
-Very good understanding of electromigration and how to layout a block with high reliability
-Appreciation and knowledge of parasitic associated with a layout.
-Knowledge of Cadence SKILL language and PCELL development.

If you are suited and interested, please can you send me your updated CV and the best number to reach you on.