Senior Staff Engineer Verification

Dealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -PartialIn your new role you will:Behavioral modeling: Verilog, Wreal or SV-RNM -FullAMS Verification for SoC or IPs -FullTest plan preparation as per the dynamics of product specifications - FullDealing challenges with AMS methodologies of Cadence: irun/xrun or Synopsys: XA-VCS or Mentor Eldo ADMS -PartialTestcase Debug & proposing new scenarios - PartialHandling project dynamics on scope, schedule and effort – coming up with alternative verification plans- FullSelf-motivated to drive new scope expansion proposals mapping to business valueMentoring junior engineers in creating problem solving mindsetEstablishing cross collaboration with other domains and coming up with proposals in enhancing product development working approachesYou are best equipped for this task if you have:Bachelors with 9+ years of experienceMentoring: Technical mentoring for junior engineers. Instigate thought-provoking culture.Analog: Functional spec understanding of standard power management blocks, clock circuits, and data converters. Loop analysis is an added advantageHDL/HVL: Verilog/Verilog-ams, SV/UVM added advantageTools: Cadence Xcelium + spectre/ Synopsys XA-VCS/ Mentor Eldo ADMSAutomation: Perl/python/shellSchedule and result oriented execution mindset, flexible in working as per the project scope needs, Exploring and experimentation for continuous methodology improvements