Senior Verification Engineer

Senior Verification Engineer Are you an experienced verification engineer looking to take the next step in your career? Are you eager to contribute to the development of cutting-edge designs in ultra-low power applications? If so, this could be the perfect opportunity for you. We are seeking a Senior Verification Engineer to join our digital and mixed-signal design verification team. You will play a key role in verifying state-of-the-art designs and contributing to the success of innovative, ultra-low power projects.   As a Senior Verification Engineer , you will: Develop project verification strategies and create UVM testbench frameworks. Build behavioural models and perform verification of ultra-low power digital designs using UVM methodology (SystemVerilog). Drive enhancements in verification methodologies and environments within the organisation. Manage and mentor a team of junior digital verification engineers. Collaborate with international teams in the US and Switzerland to share best practices and improve synergy in verification methodologies. Generate industrial test patterns to ensure robust and reliable designs. To be successful as a Senior Verification Engineer , you should have: Experience with digital verification methodologies for integrated circuits. Expertise in building testbenches based on UVM methodology. Knowledge of VHDL and all stages of digital verification (RTL, gate-level). Fluency in written and spoken English.   The following would be advantageous: Knowledge of wireless systems and communication protocols (HF, UHF, Bluetooth). Familiarity with TCL or Perl scripting. Knowledge of formal verification techniques. This is an exceptional opportunity for a Senior Verification Engineer who is ready to embrace exciting challenges and contribute to pioneering developments in the field of ultra-low power design verification. If you would like to find out more, please contact Lucy Edmondson at IC Resources.