Sr. Manager for PROCESS INTEGRATION ENGINEERING

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.JR54371 Sr. Manager for PROCESS INTEGRATION ENGINEERINGAs a Sr. manager at Micron Technology, Inc., you will be working with TD/AMD/DFM/CPIE and OMT PI/PEE responsible for cross-tech DRAM technologies Layout/OPC/CMP weakness and process optimizations to improve product quality and reliability, leading and participating in NPI and HVM baseline yield improvement activities, handling new reticle tapeout pre- and -post checks, process margin up, and new defense line setup. This position requires at least 10 years working experience in FE process with 8 years in process integration. Experience and knowledge in Layout edit/GDS view/OPC/DRC/DFM related areas is a plus.Responsibilities and Tasks:• Bridging TD/AMD/Designer with Fab PEE/PI for layout/reticle edit to eliminate process/layout weak points and process margin up.• Reticle edit (revision) sanity check• Cross-fabs baseline issues solution provider• Idendity layout weakness and provide counter proposals to TD/AMD• DFM related protocals/BP setup for fabs to follow up• AAL/NUDD/Chop layers sanity checks for NPI