Verification Application Engineer

Verification Application Engineer Are you ready to take on a challenging role as a Verification Application Engineer ? This position offers the opportunity to work independently while collaborating with a talented team to resolve customer challenges, support technology adoption, and identify both opportunities and risks. As a Verification Application Engineer , your role will encompass: Providing direct technical pre- and post-sales support, leveraging a strong technical understanding of the complete verification flow. Participating in technical campaigns to assist customers in adopting cutting-edge verification technology. Developing a deep understanding of customer needs and working closely with the sales team to define and adapt strategies accordingly. Performing methodology assessments to enhance design and verification methodologies through advanced technology and services. Assisting customers in adopting tools and methodologies by offering comprehensive knowledge and expertise. To excel as a Verification Application Engineer , candidates should possess: Proficiency in hardware design and verification languages, including Verilog, VHDL, SystemVerilog, and UVM. A strong understanding of: Common verification flows and methodologies (UVM, Coverage-Driven Verification, Assertion-Based Verification, Low-Power Verification, and Software-Driven Verification). Protocols such as AMBA, Ethernet, USB, PCIe, and MIPI (not all required). Unix/Linux environments, including scripting languages. Advantageous experience includes: Hardware emulation or prototyping. Digital mixed-signal simulation using real modelling. Formal property checking (PSL or SVA). Familiarity with languages such as UPF, C/C++, SystemC, TLM, or Specman e. Understanding of the full SoC design flow. For more information, or to apply, please contact Lucy Edmondson at IC Resources.